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12-Bit, 170 MSPS/210 MSPS 3.3 V A/D Converter AD9430
FEATURES SNR = 65 dB @ fIN up to 70 MHz @ 210 MSPS ENOB of 10.6 @ fIN up to 70 MHz @ 210 MSPS (-0.5 dBFS) SFDR = 80 dBc @ fIN up to 70 MHz @ 210 MSPS (-0.5 dBFS) Excellent Linearity: DNL = 0.3 LSB (Typical) INL = 0.5 LSB (Typical) 2 Output Data Options: Demultiplexed 3.3 V CMOS Outputs Each @ 105 MSPS Interleaved or Parallel Data Output Option LVDS at 210 MSPS 700 MHz Full Power Analog Bandwidth On-Chip Reference and Track-and-Hold Power Dissipation = 1.3 W Typical @ 210 MSPS 1.5 V Input Voltage Range 3.3 V Supply Operation Output Data Format Option Data Sync Input and Data Clock Output Provided Clock Duty Cycle Stabilizer APPLICATIONS Wireless and Wired Broadband Communications Cable Reverse Path Communications Test Equipment Radar and Satellite Subsystems Power Amplifier Linearization PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM
SENSE VREF AGND DRGND DRVDD AVDD
AD9430
SCALABLE REFERENCE
VIN+ TRACKAND-HOLD VIN-
ADC 12-BIT PIPELINE CORE
LVDS OUTPUTS 12 DATA, OVERRANGE IN LVDS OR 2-PORT CMOS
CMOS OUTPUTS DS+ DS- CLK+ CLK- CLOCK MANAGEMENT SELECT CMOS OR LVDS
DCO+ DCO-
S1
S2
S4
S5
The AD9430 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates up to a 210 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and reference, are included on the chip to provide a complete conversion solution. The ADC requires a 3.3 V power supply and a differential ENCODE clock for full performance operation. The digital outputs are TTL/CMOS or LVDS compatible and support either twos complement or offset binary format. Separate output power supply pins support interfacing with 3.3 V or 2.5 V CMOS logic. Two output buses support demultiplexed data up to 105 MSPS rates in CMOS mode. A data sync input is supported for proper output data port alignment in CMOS mode and a data clock output is available for proper output data timing. In LVDS mode, the chip provides data at the ENCODE clock rate. Fabricated on an advanced BiCMOS process, the AD9430 is available in a 100-lead surface-mount plastic package (100 e-PAD TQFP) specified over the industrial temperature range (-40C to +85C). REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
1. High Performance--Maintains 65 dB SNR @ 210 MSPS with a 65 MHz input. 2. Low Power--Consumes only 1.3 W @ 210 MSPS. 3. Ease of Use--LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample/hold provide flexibility in system design. Use of a single 3.3 V supply simplifies system power supply design. 4. Out of Range (OR)--The OR output bit indicates when the input signal is beyond the selected input range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD9430-SPECIFICATIONS
DC SPECIFICATIONS Full Scale = 1.536 V, LVDS Output Mode, unless otherwise noted.)
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Out (VREF) REFERENCE Reference Out (VREF) Output Current1 IVREF Input Current2 ISENSE Input Current2 ANALOG INPUTS (VIN+, VIN-) Differential Input Voltage Range (S5 = GND) Differential Input Voltage Range (S5 = AVDD) Input Common-Mode Voltage Input Resistance Input Capacitance POWER SUPPLY (LVDS Mode) AVDD DRVDD Supply Currents IANALOG (AVDD = 3.3 V)4 IDIGITAL (DRVDD = 3.3 V)4 Power Dissipation4 Power Supply Rejection POWER SUPPLY (CMOS Mode) AVDD DRVDD Supply Currents IAVDD (AVDD = 3.3 V)5 IDRVDD (DRVDD = 3.3 V)5 Power Dissipation5 Power Supply Rejection
3
(AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = -40 C, TMAX = +85 C, fIN = -0.5 dBFS, Internal Reference,
AD9430-170 Typ 12 Full 25C 25C 25C Full 25C Full Full Full Full 25C 25C 25C 25C Full Full Full Full 25C Full Full Full Full Full 25C Full Full Full Full Full 25C VI I I I VI I VI V V V I IV I I V V VI VI V IV IV VI VI VI V IV IV IV IV IV V 3.1 3.0 1.15 Guaranteed -3 -5 -1 -1 -1.5 -2.25 0.3 0.3 0.5 0.5 58 0.02 +0.12/-0.24 1.235 1.3 3.0 20 5.0 1.15 +3 +5 +1 +1.5 +1.5 +2.25 -3 -5 -1 -1 -1.75 -2.5 Guaranteed 0.3 0.3 0.3 0.3 58 0.02 +0.12/-0.24 1.235 1.3 3.0 20 5.0 +3 +5 +1 +1.5 +1.75 +2.5 mV % FS LSB LSB LSB LSB V/C %/C mV/C V mA A mA V V V k pF V V mA mA W mV/V V V mA mA W mV/V AD9430-210 Typ Max
Temp
Test Level Min
Max
Min
Unit Bits
1.6 1.536 0.766 2.8 3 5 3.3 3.3 335 55 1.29 -7.5 3.3 3.3 335 24 1.1 -7.5
1.6 1.536 0.766 2.8 3 5 3.3 3.3 390 55 1.5 -7.5 3.2 3.0 3.3 3.3 390 30 1.3 -7.5
2.65 2.2
2.9 3.3
2.65 2.2
2.9 3.3
3.1 3.0
3.6 3.6 372 62 1.43
3.2 3.0
3.6 3.6 450 62 1.7
3.6 3.6 372 30
3.6 3.6 450 30
NOTES 1 Internal reference mode; SENSE = Floats. 2 External reference mode; SENSE = DRVDD, VREF driven by external 1.23 V reference. 3 S5 (Pin 1) = GND. See Analog Input section. S5 = GND in all dc, ac tests unless otherwise specified. 4 IAVDD and IDRVDD are measured with an analog input of 10.3 MHz, -0.5 dBFS, sine wave, rated ENCODE rate, and in LVDS output mode. See Typical Performance Characteristics and Applications sections for IDRVDD. Power consumption is measured with a dc input at rated ENCODE rate in LVDS output mode. 5 IAVDD and IDRVDD are measured with an analog input of 10.3 MHz, -0.5 dBFS, sine wave, rated ENCODE rate, and in CMOS output mode. See Typical Performance Characteristics and Applications sections for IDRVDD. Power consumption is measured with a dc input at rated ENCODE rate in CMOS output mode. Specifications subject to change without notice.
-2-
REV. A
AD9430 AC SPECIFICATIONS1 Full Scale = 1.536 V, LVDS Output Mode, unless otherwise noted.)
Parameter SNR Analog Input @ -0.5 dBFS 10 MHz 70 MHz 100 MHz 240 MHz 10 MHz 70 MHz 100 MHz 240 MHz Temp 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C Test Level Min I I V V I I V V I I V V I I V V I I V V V V 63.5 63 AD9430-170 Typ 65 65 65 61 65 65 65 60 10.6 10.6 10.6 9.8 -85 -85 -77 -63 -87 -87 -77 -63 -75 700 -75 -75
(AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = -40 C, TMAX = +85 C, fIN = -0.5 dBFS, Internal Reference,
AD9430-210 Typ Max 64.5 64.5 64.5 61 64.5 64.5 64.5 60 10.5 10.5 10.5 9.8 -84 -84 -77 -63 -87 -87 -77 -63 -75 700 -74 -74
Max
Min 62.5 62.5
Unit dB dB dB dB dB dB dB dB Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc MHz
SINAD Analog Input @ -0.5 dBFS
63.5 63
62.5 62.5
EFFECTIVE NUMBER OF BITS (ENOB) 10 MHz 70 MHz 100 MHz 240 MHz WORST HARMONIC (2nd or 3rd) Analog Input @ -0.5 dBFS 10 MHz 70 MHz 100 MHz 240 MHz WORST HARMONIC (4th or Higher) Analog Input @ -0.5 dBFS 10 MHz 70 MHz 100 MHz 240 MHz TWO-TONE IMD2 F1, F2 @ -7 dBFS ANALOG INPUT BANDWIDTH
10.2 10.2
10.2 10.2
-78 -78
-77 -77
NOTES 1 All ac specifications tested by driving CLK+ and CLK- differentially. 2 F1 = 28.3 MHz, F2 = 29.3 MHz. Specifications subject to change without notice.
REV. A
-3-
AD9430 DIGITAL SPECIFICATIONS
Parameter ENCODE AND DS INPUTS (CLK+, CLK-, DS+, DS-)1 Differential Input Voltage2 Common-Mode Voltage3 Input Resistance Input Capacitance LOGIC INPUTS (S1, S2, S4, S5) Logic "1" Voltage Logic "0" Voltage Logic "1" Input Current Logic "0" Input Current Input Resistance Input Capacitance LOGIC OUTPUTS (CMOS Mode) Logic "1" Voltage4 Logic "0" Voltage4 LOGIC OUTPUTS (LVDS Mode)4, 5 VOD Differential Output Voltage VOS Output Offset Voltage Output Coding
(AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = -40 C, TMAX = +85 C, unless otherwise noted.)
Temp Test Level Min AD9430-170 Typ Max Min AD9430-210 Typ Max Unit
Full Full Full 25C Full Full Full Full 25C 25C Full Full Full Full
IV VI VI V IV IV VI VI V V IV IV VI VI
0.2 1.375 3.2
1.5 5.5 4
0.2 1.575 1.375 1.5 6.5 3.2 5.5 4 2.0 0.8 190 10
1.575 6.5
V V k pF V V A A k pF V
2.0
0.8 190 10 30 4 DRVDD - 0.05
30 4 DRVDD - 0.05 0.05
0.05
V
247 454 247 454 mV 1.125 1.375 1.125 1.375 V Twos Complement or Binary Twos Complement or Binary
NOTES 1 ENCODE and DS inputs identical on chip. See Equivalent Circuits section. 2 All ac specifications tested by driving CLK+ and CLK- differentially, |(CLK+) - (CLK-)| > 200 mV. 3 ENCODE inputs' common mode can be externally set, such that 0.9 V < ENC < 2.6 V. 4 Digital output logic levels: DRVDD = 3.3 V, CLOAD = 5 pF. 5 LVDS RTERM = 100 , LVDS output current set resistor = 3.74 k (1% tolerance). Specifications subject to change without notice.
SWITCHING SPECIFICATIONS (AVDD = 3.3 V, DRVDD = 3.3 V, T
Parameter (Conditions) Maximum Conversion Rate1 Minimum Conversion Rate1 CLK+ Pulsewidth High (tEH)1 CLK+ Pulsewidth Low (tEL)1 DS Input Setup Time (tSDS)2 DS Input Hold Time (tHDS)2 OUTPUT (CMOS Mode) Valid Time (tV) Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) DCO Propagation Delay (tCPD) Data to DCO Skew (tPD - tCPD) Interleaved Mode (A, B Latency) Parallel Mode (A, B Latency) OUTPUT (LVDS Mode) Valid Time (tV) Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) DCO Propagation Delay (tCPD) Data to DCO Skew (tPD - tCPD) Latency Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Out of Range Recovery Time (CMOS and LVDS) Temp Full Full Full Full Full Full Full Full 25C 25C Full Full Full Full Full Full 25C 25C Full Full Full 25C 25C 25C Test Level VI V IV IV IV IV IV IV V V IV IV IV IV VI VI V V VI IV IV V V V Min 170 2 2 -0.5 1.75 2
MIN
= -40 C, TMAX = +85 C, unless otherwise noted.)
Max 40 12.5 12.5 Min 210 2 2 -0.5 1.75 2 40 12.5 12.5 AD9430-210 Typ Max Unit MSPS MSPS ns ns ns ns ns ns ns ns ns ns Cycles Cycles ns ns ns ns ns ns Cycles ns ps rms 1 Cycles
AD9430-170 Typ
-0.5
3.8 1 1 3.8 0 14, 14 15, 14
5 5 +0.5
-0.5
3.8 1 1 3.8 0 14, 14 15, 14
5 5 +0.5
2.0 3.2 0.5 0.5 2.7 0.5 14 1.2 0.25 1 4.3 3.8 0.8
2.0 3.2 0.5 0.5 2.7 0.5 14 1.2 0.25 4.3 3.8 0.8
1.8 0.2
1.8 0.2
NOTES 1 All ac specifications tested by driving CLK+ and CLK- differentially. 2 DS inputs used in CMOS mode only. Specifications subject to change without notice.
-4-
REV. A
AD9430
N-1 AIN N N+1
tEL tEH
CLK+ CLK- 1/fS
tPD
DATA OUT N-14 N-13 14 CYCLES DCO+ DCO- N N+1
tCPD
Figure 1. LVDS Timing Diagram
CLK+ CLK- DS+ DS-
tHDS
INTERLEAVED DATA OUT PORT A DA11-DA0 STATIC
tSDS tPD
INVALID N N+2
14 CYCLES
tV
PORT B DB11-DB0
STATIC
INVALID
INVALID
N+1
N+3
PARALLEL DATA OUT PORT A DA11-DA0 STATIC INVALID INVALID N N+2
PORT B DB11-DB0
STATIC
INVALID
INVALID
N+1
N+3
tCPD
DCO- STATIC DCO+
Figure 2. CMOS Timing Diagram
REV. A
-5-
AD9430
ABSOLUTE MAXIMUM RATINGS 1 EXPLANATION OF TEST LEVELS Test Level
AVDD, DRVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Analog Inputs . . . . . . . . . . . . . . . . . -0.5 V to AVDD + 0.5 V Digital Inputs . . . . . . . . . . . . . . . . -0.5 V to DRVDD + 0.5 V REFIN Inputs . . . . . . . . . . . . . . . . . -0.5 V to AVDD + 0.5 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150C 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25C/W, 32C/W JA
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2 Typical JA = 32C/W (heat slug not soldered); typical JA = 25C/W (heat slug soldered), for multilayer board in still air with solid ground plane.
I. II.
100% production tested. 100% production tested at 25C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
ORDERING GUIDE
Model AD9430BSV-170 AD9430BSV-210 AD9430/PCB-LVDS AD9430/PCB-CMOS
Temperature Range -40C to +85C -40C to +85C 25C 25C
Package Option e-PAD TQFP-100 e-PAD TQFP-100 Evaluation Board (LVDS Mode) Evaluation Board (CMOS Mode)
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9430 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
-6-
REV. A
AD9430
PIN FUNCTION DESCRIPTIONS (CMOS Mode)
Pin Number 1 2, 7, 42, 43, 65, 66, 68 3 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100 5 6 8, 14, 15, 18, 19, 24, 27, 28, 29, 34, 39, 40, 88, 89, 90, 94, 95, 98, 99 10 11 21 22 32 33 36 37 44 45 46 47, 54, 62, 75, 83 48, 53, 61, 67, 74, 82 49 50 51 52 55 56 57 58 59 60 63 64 69 70 71 72 73 76 77 78 79 80 81 84 85
Mnemonic S5 DNC S4 AGND* S2 S1 AVDD SENSE VREF VIN+ VIN- DS+ DS- CLK+ CLK- DB0 DB1 DB2 DRVDD DRGND* DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 OR_B DCO- DCO+ DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 OR_A
Function Full-Scale Adjust Pin. AVDD sets fS = 0.768 V p-p differential, GND sets fS = 1.536 V p-p differential. Do Not Connect Interleaved, Parallel Select Pin. High = interleaved. Analog Ground Output Mode Select. Low = dual-port CMOS, High = LVDS. Data Format Select. Low = binary, High = twos complement. 3.3 V Analog Supply Reference Mode Select Pin, Float for Internal Reference Operation 1.235 Reference I/O - Function Dependent on SENSE Analog Input - True Analog Input - Complement Data Sync (Input) - True. Tie low if not used. See Timing Diagram. Data Sync (Input) - Complement. Tie high if not used. Clock Input - True Clock Input - Complement B Port Output Data Bit (LSB) B Port Output Data Bit B Port Output Data Bit 3.3 V Digital Output Supply (3.0 V to 3.6 V) Digital Output Ground B Port Output Data Bit B Port Output Data Bit B Port Output Data Bit B Port Output Data Bit B Port Output Data Bit B Port Output Data Bit B Port Output Data Bit B Port Output Data Bit B Port Output Data Bit (MSB) B Port Overrange Data Clock Output - Complement Data Clock Output - True A Port Output Data Bit (LSB) A Port Output Data Bit A Port Output Data Bit A Port Output Data Bit A Port Output Data Bit A Port Output Data Bit A Port Output Data Bit A Port Output Data Bit A Port Output Data Bit A Port Output Data Bit A Port Output Data Bit A Port Output Data Bit (MSB) A Port Overrange
*AGND and DRGND should be tied together to a common ground plane.
REV. A
-7-
AD9430
PIN FUNCTION DESCRIPTIONS (LVDS Mode)
Pin Number 1 2, 42-46 3 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100 5 6 7 8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34, 39, 40, 88, 89, 90, 94, 95, 98, 99 10 11 21 22 32 36 37 47, 54, 62, 75, 83 48, 53, 61, 67, 74, 82 49 50 51 52 55 56 57 58 59 60 63 64 65 66 68 69 70 71 72 73 76 77 78 79 80 81 84 85
Mnemonic S5 DNC S4 AGND* S2 S1 LVDSBIAS AVDD SENSE VREF VIN+ VIN- GND CLK+ CLK- DRVDD DRGND* D0- D0+ D1- D1+ D2- D2+ D3- D3+ D4- D4+ DCO- DCO+ D5- D5+ D6- D6+ D7- D7+ D8- D8+ D9- D9+ D10- D10+ D11- D11+ OR- OR+
Function Full-Scale Adjust Pin. AVDD sets fS = 0.768 V p-p differential, GND sets fS = 1.536 V p-p differential. Do Not Connect Control Pin for CMOS Mode. Tie low when operating in LVDS mode. Analog Ground Output Mode Select. GND = dual-port CMOS; AVDD = LVDS. Data Format Select. GND = binary, AVDD = twos complement. Set Pin for LVDS Output Current. Place 3.7 k resistor terminated to ground. 3.3 V Analog Supply Reference Mode Select Pin, Float for Internal Reference Operation 1.235 Reference I/O - Function Dependent on SENSE Analog Input - True Analog Input - Complement Data Sync (Input) - Not Used in LVDS Mode. Tie to GND. Clock Input - True (LVPECL Levels) Clock Input - Complement (LVPECL Levels) 3.3 V Digital Output Supply (3.0 V to 3.6 V) Digital Output Ground D0 Complement Output Bit (LSB) D0 True Output Bit (LSB) D1 Complement Output Bit D1 True Output Bit D2 Complement Output Bit D2 True Output Bit D3 Complement Output Bit D3 True Output Bit D4 Complement Output Bit D4 True Output Bit Data Clock Output - Complement Data Clock Output - True D5 Complement Output Bit D5 True Output Bit D6 Complement Output Bit D6 True Output Bit D7 Complement Output Bit D7 True Output Bit D8 Complement Output Bit D8 True Output Bit D9 Complement Output Bit D9 True Output Bit D10 Complement Output Bit D10 True Output Bit D11 Complement Output Bit D11 True Output Bit Overrange Complement Output Bit Overrange True Output Bit
*AGND and DRGND should be tied together to a common ground plane.
-8-
REV. A
AD9430
PIN CONFIGURATIONS
100 AGND 98 AVDD 89 AVDD 88 AVDD 82 DRGND 83 DRVDD 97 AGND 96 AGND 93 AGND 92 AGND 91 AGND 87 AGND 99 AVDD 95 AVDD 94 AVDD 90 AVDD 86 AGND 85 OR_A 84 DA11 81 DA10 80 DA9 79 DA8 78 DA7 77 DA6 76 DA5 75 DRVDD 74 DRGND 73 DA4 72 DA3 71 DA2 70 DA1 69 DA0 68 DNC 67 DRGND 66 DNC 65 DNC 64 DCO+ 63 DCO- 62 DRVDD 61 DRGND 60 OR_B 59 DB11 58 DB10 57 DB9 56 DB8 55 DB7 54 DRVDD 53 DRGND 52 DB6 51 DB5 AVDD 28 AVDD 29 AGND 26 AVDD 27 AGND 30 AGND 31 DS+ 32 DS- 33 AVDD 34 CLK- 37 AGND 38 AVDD 39 AGND 35 CLK+ 36 AVDD 40 AGND 41 DNC 42 DNC 43 DB2 46 DRVDD 47 DRGND 48 DB3 49 DB4 50 DB0 44 DB1 45
S5 DNC S4 AGND S2 S1 DNC AVDD AGND
1 2 3 4 5 6 7 8 9
SENSE 10 VREF 11 AGND 12 AGND 13 AVDD 14 AVDD 15 AGND 16 AGND 17 AVDD 18 AVDD 19 AGND 20 VIN+ 21 VIN- 22 AGND 23 AVDD 24 AGND 25
AD9430
CMOS PINOUT TOP VIEW (Not to Scale)
CMOS Dual-Mode Pinout
100 AGND 99 AVDD 98 AVDD 89 AVDD 88 AVDD 82 DRGND 84 OR- 83 DRVDD 97 AGND 96 AGND 95 AVDD 94 AVDD 93 AGND 92 AGND 91 AGND 90 AVDD 87 AGND 86 AGND 85 OR+ 81 D11+ 80 D11- 79 D10+ 78 D10- 77 D9+ 76 D9-
S5 DNC S4 AGND S2 S1 LVDSBIAS AVDD AGND
1 2 3 4 5 6 7 8 9
75 DRVDD 74 DRGND 73 D8+ 72 D8- 71 D7+ 70 D7- 69 D6+ 68 D6- 67 DRGND 66 D5+ 65 D5- 64 DCO+ 63 DCO- 62 DRVDD 61 DRGND 60 D4+ 59 D4- 58 D3+ 57 D3- 56 D2+ 55 D2- 54 DRVDD 53 DRGND 52 D1+ 51 D1-
AVDD 28 AVDD 29 AGND 26 AGND 30 AGND 31 AVDD 27 GND 32 AVDD 33 CLK- 37 AGND 38 AVDD 39 AVDD 40 AVDD 34 AGND 35 CLK+ 36 AGND 41 DNC 42 DNC 43 DNC 44 DNC 45 DNC 46 DRVDD 47 DRGND 48 D0- 49 D0+ 50
SENSE 10 VREF 11 AGND 12 AGND 13 AVDD 14 AVDD 15 AGND 16 AGND 17 AVDD 18 AVDD 19 AGND 20 VIN+ 21 VIN- 22 AGND 23 AVDD 24 AGND 25
AD9430
LVDS PINOUT TOP VIEW (Not to Scale)
REV. A
LVDS Mode Pinout -9-
AD9430
DEFINITIONS Analog Bandwidth Harmonic Distortion, Second
The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.
Aperture Delay
The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc.
Integral Nonlinearity
The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit.
Minimum Conversion Rate
The sample-to-sample variation in aperture delay.
Crosstalk
Coupling onto one channel being driven by a low level (-40 dBFS) signal when the adjacent interfering channel is driven by a fullscale signal.
Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance
The ENCODE rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The ENCODE rate at which parametric testing is performed.
Output Propagation Delay
The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer.
Differential Analog Input Voltage Range
The delay between a differential crossing of CLK+ and CLK- and the time when all output data bits are within valid logic levels.
Noise (for Any Range within the ADC)
Calculated as follows:
FS dBm - SNRdBc - Signal dBFS VNOISE = Z x 0.001 x 10 10
The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 out of phase. Peak-to-peak differential is computed by rotating the input's phase 180 and again taking the peak measurement. The difference is then computed between both peak measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB)
where Z is the input impedance, FS is the full scale of the device for the frequency in question, SNR is the value of the particular input level, and Signal is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise.
Power Supply Rejection Ratio
Calculated from the measured SNR based on the equation: ENOB = SNR MEASURED - 1.76 dB 6.02
The ratio of a change in input offset voltage to a change in power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
ENCODE Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time the ENCODE pulse should be left in logic 1 state to achieve rated performance; pulsewidth low is the minimum time the ENCODE pulse should be left in low state. See timing implications of changing tENCH in the Application Notes, Encode Input section. At a given clock rate, these specifications define an acceptable ENCODE duty cycle.
Full-Scale Input Power
The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
Expressed in dBm. Computed using the following equation: 2 VFULLSCALERMS = 10 log Z INPUT 0.001
The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered) or dBFS (always related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
PowerFULLSCALE
The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dBc.
Two-Tone SFDR
Gain Error
The difference between the measured and ideal full-scale input voltage range of the ADC.
The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale). -10- REV. A
AD9430
Worst Other Spur Out-of-Range Recovery Time
The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dBc.
Transient Response Time
The time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
The time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale.
EQUIVALENT CIRCUITS
AVDD
K
FULL SCALE S5 = 0 --> K = 1.24 S5 = 1 --> K = 0.62 0.1 F VREF
12k CLK+ OR DS+ 150 10k
12k CLK- OR DS- 150 10k
-+ 1V A1 200
1k DISABLE A1 VDD
SENSE
Figure 3. ENCODE and DS Inputs
AVDD 3.5k 3.5k
Figure 6. VREF, SENSE I/O
DRVDD
VIN+ 20k 20k
VIN-
DX
Figure 4. Analog Inputs Figure 7. Data Outputs (CMOS Mode)
VDD
DRVDD
S1, S2, S4, S5 30k
V DX- V
V DX+ V
Figure 5. S1-S5 Inputs Figure 8. Data Outputs (LVDS Mode)
REV. A
-11-
AD9430-Typical Performance Characteristics (Charts at 170 MSPS, 210 MSPS for -170, -210 grades, respectively.)
0 -10 -20 -30 -40 SNR = 65.2dB SINAD = 65.1dB H2 = -88.8dBc H3 = -88.1dBc SFDR = 87dBc
0 -10 -20 -30
dB
SNR = 62.99dBFS SINAD = 61.45dBFS H2 = -66.8dBc H3 = -82.5dBc SFDR = 66.1dBc
-40 -50 -60 -70 -80 -90
dB
-50 -60 -70 -80 -90 -100 0 10 20 30 40 MHz 50 60 70 80 85
-100 0 10 20 30 40 MHz 50 60 70 80 85
TPC 1. FFT: fS = 170 MSPS, AIN = 10.3 MHz @ -0.5 dBFS, LVDS Mode
TPC 4. FFT: fS = 170 MSPS, AIN = 10.3 MHz @ -0.5 dBFS, Single-Ended Input, 0.76 V Input Range, LVDS Mode
0 -10 -20 -30 -40
dB
0
SNR = 65.1dB SINAD = 64.9dB FUND = -0.50dBFS H2 = -88.6dBc H3 = -94.6dBc SFDR = 85.9dBc
-10 -20 -30 -40
dB
SNR = 63.6dB SINAD = 62.9dB H2 = -82.5Bc H3 = -78.6Bc SFDR = 77.7Bc
-50 -60 -70 -80 -90 -100 0 10 20 30 40 MHz 50 60 70 80 85
-50 -60 -70 -80 -90 -100 0 15 30 45 MHz 60 75 90 105
TPC 2. FFT: fS = 170 MSPS, AIN = 65 MHz @ -0.5 dBFS, LVDS Mode
TPC 5. FFT: fS = 210 MSPS, AIN = 10.3 MHz @ -0.5 dBFS, LVDS Mode, Full Scale = 1.536 V
0 -10 -20 -30 -40
dB
0
SNR = 64.93dB SINAD = 64.85dB FUND = -0.44dBFS H2 = -92.1dBc H3 = -90.1dBc SFDR = 75.6dBc
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100
SNR = 63.1dB SINAD = 62.8dB H2 = -81.1Bc H3 = -76.6dBc SFDR = 71.1dBc
dB
-50 -60 -70 -80 -90 -100 0 10 20 30 40 50 MHz 60 70 80 85
0
15
30
45 MHz
60
75
90
105
TPC 3. FFT: fS = 170 MSPS, AIN = 65 MHz @ -0.5 dBFS, Differential, 1.5 V p-p Input Range, CMOS Mode
TPC 6. FFT: fS = 210 MSPS, AIN = 65 MHz @ -0.5 dBFS, CMOS Mode, Full Scale = 1.536 V
-12-
REV. A
AD9430
0 -10 -20 -30 -40 SNR = 63.5dB SINAD = 62.6dB H2 = -79dBc H3 = -76.1dBc SFDR = 75.2dBc 0 -10 -20 -30 -40 SNR = 63.3dB SINAD = 63.1dB H2 = -80.38dBc H3 = -81.8dBc SFDR = 80.8dBc
dB
dB
-50 -60 -70 -80 -90 -100 0 15 30 45 MHz 60 75 90 105
-50 -60 -70 -80 -90 -100 0 15 30 45 MHz 60 75 90 105
TPC 7. FFT: fS = 210 MSPS, AIN = 65 MHz @ -0.5 dBFS, LVDS Mode, Full Scale = 1.536 V
TPC 10. FFT: fS = 213 MSPS, AIN = 100 MHz @ -0.5 dBFS, LVDS Mode, Full Scale = 1.536 V
85 80 SFDR 75 70
dB
85 80 75 70 65 SNR SNR 60 SINAD 55 FULL SCALE = 1.5 SINAD 50 45 40 0 50 100 150 200 AIN - MHz 250 300 350 400 0 50 100 150 200 AIN - MHz 250 300 350 400 FULL SCALE = 0.75
65
dB
60 55 50 45 40
TPC 8. SNR, SINAD, and SFDR vs. AIN Frequency; fS = 210 MSPS, AIN @ -0.5 dBFS, LVDS Mode, Full Scale = 1.536 V
TPC 11. SNR, and SINAD vs. AIN Frequency; fS = 210 MSPS, AIN @ -0.5 dBFS, LVDS Mode, Full Scale = 0.75 V
100 THIRD 90
100
90 THIRD
80 SFDR
dB
80 SECOND
dB
SECOND SFDR
70
70
60
60
50
50
40 0 50 100 150 200 250 AIN - MHz 300 350 400
40 0 50 100 150 200 250 AIN - MHz 300 350 400
TPC 9. Harmonic Distortion (Second and Third) and SFDR vs. AIN Frequency, fS = 170 MSPS, LVDS Mode
TPC 12. Harmonic Distortion (Second and Third) and SFDR vs. AIN Frequency, fS = 170 MSPS, CMOS Mode
REV. A
-13-
AD9430
85 80 -170 SNR 75 70 -210 SNR 65
0
-30
dB
-170 SINAD 60 -210 SINAD 55 50 45 40 0 50 100 150 200 AIN - MHz 250 300 350 400
dB
-60 SFDR = 63dBc
-90
-120 0 10 20 30 40 50 60 MHz 70 80 90 100
TPC 13. SNR, and SINAD vs. AIN Frequency; fS = 170, 210 MSPS, AIN @ -0.5 dBFS, LVDS Mode, Full Scale = 1.536 V
TPC 16. Two Tone Intermodulation Distortion (59 MHz and 60 MHz), LVDS Mode, Full Scale = 1.536 V, fS = 210 MSPS
85 80 75 SFDR 70
95 90 85 80 75 SFDR
dB
SNR
dB
70 65
65 60 55 50 45 40 0 50 100 150
SINAD
SINAD 60 55 50
200 AIN - MHz
250
300
350
400
0
50
100 MHz
150
200
250
TPC 14. SNR, and SINAD, SFDR vs. AIN Frequency; fS = 210 MSPS, AIN @ -0.5 dBFS, CMOS Mode, Full Scale = 1.536 V
TPC 17. SINAD and SFDR vs. Clock Rate (AIN = 10.3 MHz @ -0.5 dBFS, LVDS Mode), -170 Grade
0 SFDR = 75dBc -10 -20 -30
85 80 75 70
SFDR
dB
-40
SNR 65
dB
-50 -60 -70 -80 -90 -100 0 10 20 30 40 50 MHz 60 70 80 85
60 55 50 45 40 0 50
SINAD
100 MHz
150
200
250
TPC 15. Two-Tone Intermodulation Distortion (28.3 MHz and 29.3 MHz; LVDS Mode, fS = 170 MSPS)
TPC 18. SNR, and SINAD, SFDR vs. Clock Rate; (AIN = 10.3 MHz, @ -0.5 dBFS), LVDS Mode, Full Scale = 1.536 V, -210 Grade
-14-
REV. A
AD9430
400
IAVDD (ANALOG SUPPLY CURRENT) - mA
80
IDRVDD (OUTPUT SUPPLY CURRENT) - mA
80 SFDR 75
350 300 250 200 150 100 50 0 100
ANALOG SUPPLY CURRENT CMOS MODE 60 ANALOG SUPPLY CURRENT LVDS MODE 40
70
OUTPUT SUPPLY CURRENT LVDS MODE
dB
65
SNR SINAD
60
20 OUTPUT SUPPLY CURRENT CMOS MODE 10 120 140 160 180 ENCODE - MSPS 200 220
55
50 20
30
40
50
60
70
80
ENCODE POSITIVE DUTY CYCLE - %
TPC 19. IAVDD and IDRVDD vs. Clock Rate (AIN = 10.3 MHz @ -0.5 dBFS) 170 MSPS Grade, CLOAD = 5 pF
TPC 22. SNR, SINAD, and SFDR vs. ENCODE Pulsewidth High, (AIN = 10.3 MHz @ -0.5 dBFS, 210 MSPS, LVDS)
1.4
450
90 80 ANALOG SUPPLY CURRENT CMOS MODE 70 60 OUTPUT SUPPLY CURRENT LVDS MODE 50 40 30 OUTPUT SUPPLY CURRENT CMOS MODE 20 10 0 120 140 160 180 200 220 240 ENCODE - MSPS
400 350 300 250 200 150 100 50 0 100
IDRVDD (OUTPUT SUPPLY CURRENT) - mA
IAVDD (ANALOG SUPPLY CURRENT) - mA
ANALOG SUPPLY CURRENT LVDS MODE
1.2 RO = 13 1.0 TYP
VREFOUT - V
0.8 0.6 0.4 0.2 0 0 1 2 3 4 ILOAD - mA 5 6 7 8
TPC 20. IAVDD and IDRVDD vs. Clock Rate (AIN = 10.3 MHz @ -0.5 dBFS) 210 MSPS Grade, CLOAD = 5 pF
TPC 23. VREFOUT vs. ILOAD
85 80 SFDR 75
2.0 1.5 1.0 GAIN ERROR - % 0.5 0 -0.5 -1.0 -1.5 -2.0 -50
70
dB
% GAIN ERROR USING EXT REF
SNR 65 SINAD 60 55 50 10 20 30 40 50 60 70 ENCODE POSITIVE DUTY CYCLE - % 80 90
-30
-10
10 30 50 TEMPERATURE - C
70
90 95
TPC 21. SINAD and SFDR vs. Clock Pulsewidth High (AIN = 10.3 MHz @ -0.5 dBFS, 170 MSPS, LVDS)
TPC 24. Full-Scale Gain Error vs. Temperature (AIN = 10.3 MHz @ -0.5 dBFS, 170 MSPS/210 MSPS, LVDS)
REV. A
-15-
AD9430
1.250 1.00 0.75 1.245 0.50 0.25
VREF - V
1.240
LSB
1.235 1.230 1.225 2.5
0 -0.25 -0.50 -0.75 -1.00
2.7
2.9
3.1 3.3 AVDD - V
3.5
3.7
3.9
0
500
1000
1500
2000 CODE
2500
3000
3500
4000
TPC 25. VREF Output Voltage vs. AVDD
TPC 28. Typical INL Plot (AIN = 10.3 MHz @ -0.5 dBFS, 170 MSPS, LVDS)
95 THIRD 90 SECOND 85 SFDR 80
LSB dB
1.00 0.75 0.50 0.25 0
75 -0.25 70 -0.50 65 60 -50 SNR SINAD -1.00 -30 -10 10 30 50 TEMPERATURE - C 70 90 0 500 1000 1500 2000 CODE 2500 3000 3500 4000 -0.75
TPC 26. SNR, SINAD, SFDR vs. Temperature (AIN = 10.3 MHz @ -0.5 dBFS, 170 MSPS)
TPC 29. Typical DNL Plot (AIN = 10.3 MHz @ -0.5 dBFS, 170 MSPS, LVDS)
65 64 63 AVDD = 3.3 62 61 AVDD = 3.6
100 90 SFDR -dBFS 80 70 60
dB
AVDD = 3.135
dB
60 59 58
50 40 30 SFDR -dBc 80dB REFERENCE LINE
AVDD = 3.0 57 56 55 -45 -25 -5 15 35 55 75
20 10 0 -100
-90
-80
TEMPERATURE - C
-70 -60 -50 -40 -30 -20 ANALOG INPUT LEVEL - dBFS
-10
0
TPC 27. SINAD vs. Temperature, AVDD; (AIN = 70 MHz @ -0.5 dB, 210 MSPS, LVDS Mode, Full Scale = 1.536 V)
TPC 30. SFDR vs. AIN Input Level 10.3 MHz, AIN @ 170 MSPS, LVDS
-16-
REV. A
AD9430
90 80
0
-20
70 60 50
dB
SFDR dBc LVDS MODE FULL SCALE = 1.5 SFDR dBc CMOS MODE FULL SCALE = 1.5
-40
dB
40 30
-60
19.2
-80
20 80dB REFERENCE LINE 10 0 -90
-100
-80 -70 -60 -50 -40 -30 -20 -10 0
19.2
38.4 MHz
47.6
TPC 31. SFDR vs. AIN Input Level @10.3 MHz, 210 MSPS, LVDS/CMOS, Full Scale = 1.536 V
TPC 34. W-CDMA Four Channels Centered at 38.4 MHz, fS = 153.6 MHz, LVDS, Full Scale = 1.536 V
90 80 70 60 50
dB
90 80 SNR 70 SFDR
SFDR dBc LVDS MODE FULL SCALE = 1.5
dB
60 SINAD 50 40
40 30 20
SFDR dBc LVDS MODE FULL SCALE = 0.75
30 20
80dB REFERENCE LINE 10 0 -90
10 0
-80
-70
-60
-50
-40
-30
-20
-10
0
0
0.500
1.000
1.500
2.000
2.500
FULL-SCALE RANGE - V
TPC 32. SFDR vs. AIN Input Level @10.3 MHz, 210 MSPS, LVDS, Full Scale = 0.75 V/1.536 V
TPC 35. SNR, and SINAD, SFDR vs. Full-Scale Range, S5 = 0, Full-Scale Range Varied by Adjusting VREF, 170 MSPS
0 -20 NPR = 56.95dB ENCODE = 170MSPS NOTCH @ 19MHz
4.5
NOISE INPUT LEVEL - dB
-40 -60
4.0
ns
-80 -100
3.5 TPD
3.0
-120 -140 2.65 21.25 MHz 42.5
TCPD
2.5 -40
-20
0
20 40 TEMPERATURE - C
60
80
100
TPC 33. Noise Power Ratio Plot
TPC 36. Propagation Delay vs. Temperature, LVDS, 170 MSPS/210 MSPS
REV. A
-17-
AD9430
4.5
900 800
TCPD (CLOCKOUT RISING)
1.4 1.3 VOS 1.2 1.1 1.0 0.9 VOD 0.8 0.7 0.6 0.5 14
VOS - V
4.0
700 600
VDIF - mV TPDF (DATA FALLING)
500 400 300 200 100
ns
3.5
TPDR (DATA RISING) 3.0
2.5 -40
-20
0
20
40
60
80
100
0 0
2
4
6 RSET - k
8
10
12
TEMPERATURE - C
TPC 37. Propagation Delay vs. Temperature, CMOS, 170 MSPS/210 MSPS
TPC 38. LVDS Output Swing, Common-Mode Voltage vs. RSET, Placed at LVDSBIAS, 170 MSPS/210 MSPS
APPLICATION NOTES THEORY OF OPERATION
The AD9430 architecture is optimized for high speed and ease of use. The analog inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 12-bit core. For ease of use, the part includes an on-board reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output's logic levels are user selectable as standard 3 V CMOS or LVDS (ANSI-644 compatible) via Pin S2.
ENCODE INPUT
the input without degrading performance. Jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 30 MHz nominally. The loop has a time constant associated with it that needs to be considered in applications where the clock rate can change dynamically, requiring a wait time of 1.5 s to 5 s after a dynamic clock frequency increase before valid data is available. This circuit is always on and cannot be disabled by the user. The Clock inputs are internally biased to 1.5 V (nominal) and support either differential or single-ended signals. For best dynamic performance, a differential signal is recommended. An MC100LVEL16 performs well in the circuit to drive the Clock inputs, as illustrated in Figure 9. Note that for this low voltage PECL device, the ac coupling is optional.
0.1 F
Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock will be combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the Clock inputs of the AD9430, and the user is advised to give careful thought to the clock source. The AD9430 has an internal clock duty cycle stabilization circuit that locks to the rising edge of CLK+ and optimizes timing internally. This allows for a wide range of input duty cycles at
AD9430
CLK+
PECL GATE CLK- 0.1 F 510 510
Figure 9. Driving Clock Inputs with LVEL16
-18-
REV. A
AD9430
Table I. Output Select Coding
S1 (Data Format Select) 1 0 X X X X X
X = Don't Care
S2 (LVDS/CMOS Mode Select)1 X X 0 0 1 X X
S4 (I/P Select) X X 1 0 X X X
S5 (Full-Scale Select)2 X X X X X 1 0
Mode Twos Complement Offset Binary Dual-Mode CMOS Interleaved Dual-Mode CMOS Parallel LVDS Mode Full Scale = 0.768 V Full Scale = 1.536 V
NOTES 1 S4 used in CMOS mode only (S2 = 0). S1-S5 all have 30 k resistive pull-downs on chip. 2 S5 Full-Scale Adjust (see Analog Input section). In interleaved mode, output data on Port A is offset from output data changes on Port B by one-half output clock cycle:
Interleaved mode
Parallel mode
ANALOG INPUT
The analog input to the AD9430 is a differential buffer. For best dynamic performance, impedances at VIN+ and VIN- should match. The analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. SNR and SINAD performance will degrade significantly if the analog input is driven with a single-ended signal. A wideband transformer, such as Minicircuits' ADT1-1WT, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Both analog inputs are self-biased by an on-chip resistor divider to a nominal 2.8 V (see the Equivalent Circuits section). Special care was taken in the design of the analog input section of the AD9430 to prevent damage and corruption of data when the input is overdriven. The nominal input range is 1.5 VDIFF p-p. The nominal differential input range is 768 mV p-p 2. Note that the best performance is achieved with S5 = 0 (full-scale = 1.5). See TPC 32.
S5 = GND
S5 = AVDD
VIN+ 768mV 2.8V VIN- = 2.8V 2.8V
Figure 11. Single-Ended Analog Input Range
DS INPUTS (DS+, DS-)
VIN+
768mV 2.8V
2.8V
VIN- DIGITALOUT = ALL 1s DIGITALOUT = ALL 0s
Figure 10. Differential Analog Input Range
In CMOS output mode, the Data Sync inputs (DS+, DS-) can be used in applications requiring that a given sample will appear at a specific output port (A or B) relative to a given external timing signal. The DS inputs can also be used to synchronize two or more ADCs in a system to maintain phasing between Ports A and B on separate ADCs (in effect, synchronizing multiple DCO outputs). When DS+ is held high (DS- low), the ADC data outputs and clock do not switch and are held static. Synchronization is accomplished by the assertion (falling edge) of DS+ within the timing constraints tSDS and tHDS, relative to a clock rising edge. (On initial synchronization, tHDS is not relevant.) If DS+ falls within the required setup time (tSDS) before a given clock rising edge N, the analog value at that point in time will be digitized and available at Port A, 14 cycles later in interleaved mode. The very next sample, N + 1, will be sampled by the next rising clock edge and available at Port B, 14 cycles after that clock edge. In dual parallel mode, Port A has a 15 cycle latency and Port B has a 14 cycle latency, but data is
REV. A
-19-
AD9430
available at the same time. Driving each ADC's DS inputs by the same sync signals will accomplish this. An easy way to accomplish synchronization is by a one time sync at power-on reset. Note that when running the AD9430 in LVDS mode, set DS+ to ground and DS- to 3.3 V, as the DS inputs are relevant only in CMOS output mode, simplifying the design for some applications as well as affording superior SNR/SINAD performance at higher encode/analog frequencies.
Digital Outputs Voltage Reference
The off-chip drivers on the chip can be configured to provide CMOS or LVDS compatible output levels via Pin S2. The CMOS digital outputs (S2 = 0) are TTL /CMOS compatible for lower power consumption. The outputs are biased from a separate supply (DRVDD), allowing easy interface to external logic. The outputs are CMOS devices that will swing from ground to DRVDD (with no dc load). It is recommended to minimize the capacitive load the ADC drives by keeping the output traces short (< 1 inch, for a total CLOAD < 5 pF). When operating in CMOS mode, it is also recommended to place low value (20 ) series damping resistors on the data lines to reduce switching transient effects on performance.
LVDS Outputs
A stable and accurate 1.23 V voltage reference is built into the AD9430 (VREF). The analog input full-scale range is linearly proportional to the voltage at VREF. Note that an external reference can be used by connecting the SENSE pin to VDD (disabling internal reference) and driving VREF with the external reference source. No appreciable degradation in performance occurs when VREF is adjusted 5%. A 0.1 F capacitor to ground is recommended at the VREF pin in internal and external reference applications. Float the SENSE pin for internal reference operation.
K FULL SCALE S5 = 0 --> K = 1.24 S5 = 1 --> K = 0.62 0.1 F VREF -+ 1V A1 200 EXTERNAL 1.23V + REFERENCE
1k DISABLE A1 VDD
SENSE 3.3V
+
LVDS outputs are available when S2 = VDD and a 3.7 RSET resistor is placed at Pin 7 (LVDSBIAS) to ground. The RSET resistor current is ratioed on-chip, setting the output current at each output equal to a nominal 3.5 mA (11 3 IRSET). A 100 differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. LVDS mode facilitates interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 termination resistor as close to the receiver as possible. It is recommended to keep the trace length 1-2 inches and to keep differential output trace lengths as equal as possible.
Clock Outputs (DCO+, DCO-)
Figure 12. Using an External Reference
NPR Testing
The input ENCODE is divided by two (in CMOS mode) and available off-chip at DCO+ and DCO-. These clocks can facilitate latching off-chip, providing a low skew clocking solution (see timing diagram). The on-chip clock buffers should not drive more than 5 pF of capacitance to limit switching transient effects on performance. Note that the outputs clocks are CMOS levels when CMOS mode is selected (S2 = 0) and are LVDS levels when in LVDS mode (S2 = VDD), (requiring a 100 differential termination at receiver in LVDS mode). The output clock in LVDS mode switches at the ENCODE rate.
Noise Power Ratio Testing is a test that is commonly used to characterize the return path of cable systems where the signals are typically QAM signals with a "noise-like" frequency spectrum. NPR performance of the AD9430 was characterized in the lab yielding an effective NPR = 56.9 dB at an analog input of 19 MHz. This agrees with a theoretical maximum NPR of 57.1 dB for an 11-bit ADC at 13.6 dB backoff. The rms noise power of the signal inside the notch is compared with the rms noise level outside the notch using an FFT. Sufficiently long record lengths to guarantee a sufficient number of samples inside the notch is a requirement, as well as a high order band-stop filter that provides the required notch depth for testing.
-20-
REV. A
AD9430
AD9430 EVALUATION BOARD Voltage Reference
The AD9430 evaluation board offers an easy way to test the AD9430. It requires a clock source, an analog input signal, and a 3.3 V power supply. The clock source is buffered on the board to provide the clocks for the ADC, an on-board DAC, latches, and a data ready signal. The digital outputs and output clocks are available at two 40-pin connectors, P3 and P4. See Figure 18. The board has several different modes of operation and is shipped in the following configuration: * Offset Binary * Internal Voltage Reference * CMOS Parallel Timing * Full-Scale Adjust = Low
Power Connector
The AD9430 has an internal 1.23 V voltage reference. The ADC uses the internal reference as the default when jumpers E24-E27 and E25-E26 are left open. The full scale can be increased by placing optional resistor R3. The required value would vary with the process and needs to be tuned for the specific application. Full scale can similarly be reduced by placing R4; tuning would be required here as well. An external reference can be used by shorting the SENSE pin to 3.3 V (place jumper E26-E25). E27-E24 jumper connects the ADC VREF pin to EXT_VREF pin at the power connector.
Data Format Select
Power is supplied to the board via a detachable 12-lead power strip (three 4-pin blocks).
Table II. Power Connector
Data format select sets the output data format of the ADC. Setting DFS (E1 to E2) low sets the output format to be offset binary; setting DFS high (E1 to E3) sets the output to twos complement.
I/P
AVDD 3.3 V DRVDD 3.3 V VDL 3.3 V EXT_VREF* VCLK/V_XTAL VAMP
Analog Supply for ADC (~ 350 mA) Output Supply for ADC (~ 28 mA) Supply for Support Logic and DAC (~ 350 mA) Optional External Reference Input Supply for Clock Buffer/Optional XTAL Supply for Optional Amp
Output timing is set at E11-E13. E12 to E11 sets S4 low for parallel output timing mode. E11 to E13 sets S4 high for interleaved timing mode.
Timing Controls
Flexibility in latch clocking and output timing is accomplished by allowing for clock inversion at the timing controls section of the PCB. Each buffered clock is buffered by an XOR and can be inverted by moving the appropriate jumper for that clock.
Data Outputs
*LVEL16 clock buffer can be powered from AVDD or VCLK at E47 jumper (AVDD, DRVDD, and VDL are the minimum required power connections).
Analog Inputs
The evaluation board accepts a 1.3 V p-p analog input signal centered at ground at SMB connector J4. This signal is terminated to ground through 50 by R16. The input can be alternatively terminated at transformer T1 secondary by R13 and R14. T1 is a wideband RF transformer providing the single-ended-to-differential conversion, allowing the ADC to be driven differentially, minimizing even order harmonics. An optional second transformer, T2, can be placed following T1 if desired. This would provide some performance advantage (~1-2 dB) for high analog input frequencies (>100 MHz). If T2 is placed, two shorting traces at the pads would need to be cut. The analog signal is low-pass filtered by R41, C12, and R42, C13 at the ADC input.
Gain
The ADC digital outputs are latched on the board by four LVT574s; the latch outputs are available at the two 40-pin connectors at Pins 11-33 on P23 (Channel A) and Pins 11-33 on P3 (Channel B). The latch output clocks (data ready) are available at Pin 37 on P23 (Channel A) and Pin 37 on P3 (Channel B). The data ready clocks can be inverted at the timing controls section if needed.
: 4.6ns C1 FREQ 84.65608MHz
1
Full scale is set at E17-E19. Connecting E17 to E18 sets S5 low, full scale = 1.5 V differential; connecting E17 to E19 sets S5 high, full scale = 0.75 V differential.
ENCODE
2
The ENCODE clock is terminated to ground through 50 at SMB connector J5. The input is ac-coupled to a high speed differential receiver (LVEL16) that provides the required low jitter, fast edge rates needed for optimum performance. J5 input should be > 0.5 V p-p. Power to the EL16 is set at jumper E47. Connecting E47 to E45 powers the buffer from AVDD, connecting E47 to E46 powers the buffer from VCLK/V_XTAL.
CH1
2.00V
CH2
2.00V
M 5.00ns
CH2
Figure 13. Data Output and Clock @ 80-Pin Connector
REV. A
-21-
AD9430
DAC Outputs Optional Amplifier
Each channel is reconstructed by an on-board dual-channel DAC, an AD9753. This DAC is intended to assist in debug--it should not be used to measure the performance of the ADC. It is a current output DAC with on-board 50 termination resistors. The figure below is representative of the DAC output with a full-scale analog input. The scope setting is low bandwidth.
C1 FREQ 10.33592MHz
The footprint for transformer T2 can be modified to accept a wideband differential amplifier (AD8350) for low frequency applications where gain is required. Note that Pin 2 would need to be lifted and left floating for operation. Input transformer T1 would need to be modified to a 4:1 for impedance matching and ADC input filtering would enhance performance (see the AD8350 data sheet). SNR/SINAD performance of 61 dB/60 dB is possible and would start to degrade at about 30 MHz.
CUT TRACE
C1 p-p 448mV
1
AD8350
1
CH1
2.00mV
M 25.0ns CH1
248mV
Figure 14. DAC Output
ENCODE XTAL
CUT TRACE
An optional XTAL oscillator can be placed on the board to serve as a clock source for the PCB. Power to the XTAL is through the VCLK/VXTAL pin at the power connector. If an oscillator is used, ensure proper termination for best results. The board has been tested with a Valpey Fisher VF561 and a Vectron JN00158-163.84. Test results for the VF561 are shown in Figure 15.
0 -10 -20 -30 -40 ENCODE 163.84MHz ANALOG 65.02MHz SNR 63.93dB SINAD 63.87dB FUND -0.45dBFS 2ND -85.62dBc 3RD -91.31dBc 4TH -90.54dBc 5TH -90.56dBc 6TH -91.12dBc THD -82.21dBc SFDR 83.93dBc SAMPLES 8k NOISEFLR -100.44dBFS WORSTSP -83.93dBc
Figure 16. Using the AD8350 on the AD9430 PCB
Troubleshooting
If the board does not seem to be working correctly, try the following: * Verify power at IC pins. * Check that all jumpers are in the correct position for the desired mode of operation. * Verify VREF is at 1.23 V. * Try running clock and analog inputs at low speeds (10 MSPS/1 MHz) and monitor latch, DAC, and ADC for toggling. The AD9430 evaluation board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability, or fitness for a particular purpose.
dB
-50 -60 -70 -80 -90 -100 0
20
40 MHz
60
80
Figure 15. FFT--Using VF561 XTAL as Clock Source
3.3V + - + 3.3V - + 3.3V -
SIGNAL GENERATOR REFIN
BAND-PASS FILTER
AVDD GND ANALOG J4
DRVDD GND
VDL GND
AD9430 EVALUATION BOARD 10MHz REFOUT SIGNAL GENERATOR
DATA CAPTURE AND PROCESSING
CLOCK J5
Figure 17. Evaluation Board Connections -22-
REV. A
AD9430
Table III. Evaluation Board Bill of Materials
No. 1 2 3 4 5 6 7
Quantity Reference Designator 47 1 2 1 1 7 9 C1, C3-C11, C15-C17, C19-C29, C31-C48, C58-C62 C2 C12, C13 C14 C18 C30, C49, C63-C67 E3-E1-E2 E19-E17-E18 E13-E11-E12 E26-E25-E27-E24 E46-E47-E45 E35-E33-E34 E32-E30-E31 E29-E23-E28 E22-E16-E21 J1, J2, J3, J4, J5, J6 P3, P23 P4, P21, P22
Device Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor 3-Pin Header/Jumper 3-Pin Header/Jumper 3-Pin Header/Jumper 4-Pin Header 3-Pin Header/Jumper 3-Pin Header/Jumper 3-Pin Header/Jumper 3-Pin Header/Jumper 3-Pin Header/Jumper SMB 40-Pin Header 4-Pin Power Connector
Package 0603 0603 0603 0603 0603 CAPL
Value 0.1 F 10 pF 20 pF 0.01 F 1 F 10 F
Comments C43, C47 Not Placed Not Placed Not Placed
C30 Not Placed
8 9 10
6 2 3
SMB Post Detachable Connector 0603 0603 0603 0603 0603 0603 0603 0603 SO16RES SO16RES CD542 TQFP100 SO8NB SO14NB SO20 LQFP48 Z5.531.3425.0 25.602.5453.0 50 3.9 k 100 0 510 2 k 390 1 k 742C163221JTR 742C163220JTR Mini-Circuits ADT1-1WT ADC Clock Buffer XOR Latch DAC
J2 Not Placed Wieland Wieland R1, R13, R14 Not Placed R3, R4 Not Placed R15, R21-R24, Not Placed
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
10 3 14 5 4 1 1 7 4 8 2 1 1 1 4 1
R1, R5, R13, R14, R16, R25, R27, R28, R41, R42 R2, R3, R4 R6-R8, R10, R15, R21-R24, R33-R36, R38 R9, R11, R12, R30, R37 R17, R18, R19, R20 R26 R29 R31, R32, R39, R40, R43, R44, R45 RZ1, RZ2, RZ3, RZ4 RZ5, RZ6, RZ7, RZ8, RZ9, RZ10, RZ11, RZ12 T1, T2 U1 U2 U3 U4, U5, U6, U7 U9
Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Pack 220 Resistor Pack 22 Transformer AD9430BSV MC100LVEL16D 74LVC86 74LVT574 AD9753AST
CTS CTS T2 Not Placed
REV. A
-23-
74LVC86 U3 CLKLATA
1 16 D0 Q0 Q1 Q2 Q3 DX9 DX8 DX7 DX6 DX5 12 11 10 9 16 4 13 R4 DX10 17 3 14 R3 DX11 18 2 15 R2 DRX D1 D2 D3 D4 D5 D6 D7 GND 19 16 15 14 13 12 11 10 9 GND 10 9 8 7 6 5 4 3 2 1 2 3 R3 R4 R5 R6 R7 R8 R2 R1 GND R1 1 OUT_EN VCC 20 VDL
AD9430
P1 P2 P3 P4
1 2 3 4
GND VAMP RZ1 220 RZ8 22
VCC COUTA 3 R33 100 R10 100 74LVC86 U3 DRA
4 5 6
E35 E33 E34 E32 COUTA 6 R34 100
7
1 2 U4
GND
VDL
E20
GND VCC
COUTA R9
P1 P2 P3 P4
1 2 3 4
VCLK/ V_XTAL EXT_VREF GND VDL
DRVDD
E7
H4 MTHOLES
COUT
E30 GND 74LVC86 U3 R35 100 LVT574 11 DRB
RZ2 220 1 16 D0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 D7 10 GND Q7 CLOCK 17 16 15 14 13 12 11 18 D1 D2 D3 D4 D5 D6 19 15 14 13 12 11 10 9 GND 9 8 7 6 5 4 3 2 2 R2 R3 R4 R5 R6 R7 R8 R1 GND 1 OUT_EN VCC 20 VDL 1 2 3 4 5 6 7 8 CLKLATA R1 R2 R3 R4 R5 R6 R7 R8 16 15 14 13 12 11 10 9 DX4 DX3 DX2 DX1 DX0 DXA DXB
4 5
P21 P4 P22 PTMICA04 PTMICA04 PTMICA04
P1 P2 P3 P4
1 2 3 4
GND DRVDD GND AVDD (VCC)
H3 MTHOLES COUTAB R11
E31 E29 COUTAB 8 CLKLATB
8
R8 100 9 10
H2 COUTB MTHOLES
VCC E23 GND 74LVC86 U3 R36 100
3 4 5 6 7
H2 MTHOLES
E28 E22 COUTAB U5 E16 E21 GROUND PAD UNDER PART PLB GND GND VCC VCC GND GND VCC VCC GND GND GND VCC VCC VCC GND GND DRVDD GND R6 100 12 13
GND
R7 100
15 DM8 5 R5 Q4 14 DM7 6 R6 Q5 13 DM6 7 R7 Q6 12 DM5 8 R8 Q7 11 CLOCK CLKLATA
VCC GND
GND DRA GND DX11 DX10 DX9 DX8 DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 DXA DXB DRX P40 P38 P36 P34 P32 P30 P28 P26 P24 P22 P20 P18 P16 P14 P12 P10 P8 P6 P4 P2 P39 P37 P35 P33 P31 P29 P27 P25 P23 P21 P19 P17 P15 P13 P11 P9 P7 P5 P3 P1 GND
RZ7 22
C4OMS P23
E17 DRVDD GND
GND
E18
E14
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
VCC
8
E19
LVT574
VCC GND GND VCC GND R3 E29 E27 E26 R2 3.9k VCC GND
E13
E11
GND
E12
GND
VCC
E10
R40 1k
E8
GND EXT_VREF R4 C1 0.1 F E24 U1 COUT COUTB DRVDD GND
E9
GND
AD9430
VCC
E6
R39 1k
E4 R3, R4 OPTIONAL
RZ3 220 1 2 3 4 5 R1 R2 R3 R4 R5 GND 16 15 14 13 12 R6 6 7 8 R7 R8
U6
1 2 3 4 5 6 OUT_EN D0 D1 D2 D3 D4 VCC Q0 Q1 Q2 Q3 Q4 20 19 18 17 16 15 VDL 1 2 3 4 5
GND RZ6 22 R1 R2 R3 R4 R5 16 15 14 13 12 R6 11 10 9 GND 7 8 9 10 D5 D6 D7 Q5 Q6 Q7 GN CLOCK D LVT574 14 13 12 11 6 7 8 CLKLATA R7 R8 DRY DY11 DY10 DY9 DY8
GND VCC
E5 E3
E1
GND T2 OPTIONAL C43 0.1 F GND R41 25 GND VCC GND C13 20pF GND VCC VCC VCC GND GND VCC GND GND VCC GND GND GND CLK+ DATA SYNC J1 VCC GND E47 VCLK U2 C5 0.1 F E46 8 VCC Q 7 C36 0.1 F E45 R1 50 R5 50 GND R42 25 C47 0.1 F CLK-
T2 ADT1-1WT
E2
GND GND VCC VCC GND GND GND VCC VCC C12 GND 20pF DRVDD GND
11 10 9
T1 ADT1-1WT
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
C3 0.1 F C11 0.1 F 4 1 5 2 3 6 PRI SEC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DY7 DY6 DY5
DRVDD GND
Figure 18a. Evaluation Board Schematic -24-
RZ4 220 1 2 3 4 5 6 7 8 R1 R2 R3 R4 R5 R6 R7 R8 GND 16 15 14 13 12 11 10 9 GND
R14 29 GND
R16 50
1 4 5 2 3 6 PRI SEC
GND
J4
C7 R13 0.1 F 25
C2 10pF
GND DRB GND DY11 DY10 DY9 DY8 DY7 DY6 DY5 DY4 DY3 DY2 DY1 DY0 DYA DYB DRY
U7
1 2 3 4 5 6 7 8 9 10 OUT_EN D0 D1 D2 D3 D4 D5 D6 D7 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 20 19 18 17 16 15 14 13 12 CLOCK GN D LVT574 11 VDL 1 2 3 4 5 6 7 8
C6 0.1 F
RZ5 22 R1 R2 R3 R4 R5 R6 R7 R8 CLKLATB 16 15 14 13 12 11 10 9 DY2 DY1 DY0 DYA DYB DY4 DY3
P40 P38 P36 P34 P32 P30 P28 P26 P24 P22 P20 P18 P16 P14 P12 P10 P8 P6 P4 P2
P39 P37 P35 P33 P31 P29 P27 P25 P23 P21 P19 P17 P15 P13 P11 P9 P7 P5 P3 P1
GND
ANALOG
E15
R13, R14 OPTIONAL
C4OMS P3
ENCODE R27 50 3 DN 6 QN 4 VBB VEE 5 C8 0.1 F GND R20 510 GND R17 510 R10 510
J5 D
MC100LVEL 16 2
J2 GND C10 0.1 F R1 NOT PLACED
GND
C9 E36 R19 510 0.1 F VCC
00 R12 + C4 0.1 F C30 10 F
REV. A
GND GND
AD9430
uVCC
+
C64 10 F C16 0.1 F
C17 0.1 F
C19 0.1 F
C21 0.1 F
C20 0.1 F
C23 0.1 F
C22 0.1 F
C25 0.1 F
C24 0.1 F
C27 0.1 F
C26 0.1 F
C29 0.1 F
C28 0.1 F
C31 0.1 F
C32 0.1 F
C35 0.1 F
GND VDL +
C67 10 F C44 0.1 F C42 0.1 F
C41 0.1 F
C15 0.1 F
C37 0.1 F
GND
DRVDD
VCLK +
C65 10 F C61 0.1 F C62 0.1 F C60 0.1 F C59 0.1 F C58 0.1 F C66 10 F C14 0.1 F
VREF
VAMP
+
C63 10 F
+
C49 10 F
C48 0.1 F
GND
GND
GND
GND
GND R15 100 R38 100
VCLK 1 E/D 2 NC 3 GND VCC 6 5 OUTPUT B 4 OUTPUT VCLK R21 100
OPIN B
GND
OPIN B
GND GND
OUT- GND GND IN-
P1 R22 100 GND VCLK R23 100 P2 R24 100 AD8350
GND
8
7
6
5
OPTIONAL AMP
R38 FOR VF561 CRYSTAL
U8
IN+
ENBL
1
2
3 VCC
4 OUT+ OPIN
U10
OPTIONAL XTAL
GND
GND VAMP OPIN
J6 GND J3 VOL GND C38 0.1 F R30 0 R28 50 GND C18 1 F R29 GND 392 R25 50 GND
C34 VOL 0.1 F GND E4Z E40 E41 R44 C33 GND 0.1 F R26 2k GND 1k E39 E37 E38 R45 1k GND GND RZ12 9 10 36 35 34 33 32 31 11 12 13 14 15 16 R8 R7 R6 R5 R4 R3 R2 R1 22 8 7 6 5 4 3 2 1 DYB DYA DY0 DY1 DY2 DY3 VOL GND VOL
48
47
46
45
44
43
42
41
40
39
38
VOL GND R31 1k C40 0.1 F R32 1k C45 0.1 F GND DX11 DX10 DX9 DX8 DX7 DX6 DX5 DX4 1 2 3 4 5 6 7 8
R43 1k R37 DRA 0 VOL C46 0.1 F GND RZ9 R1 R2 R3 R4 R5 R6 R7 R8 22 RZ11 DX3 DX2 DX1 DX0 DXA DXB 1 2 3 4 5 6 7 8 R1 R2 R3 R4 R5 R6 R7 R8 22 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 GND
1 2 3 4 5 6
GND
AD9753
30 7 8 9 10 11 12 29 28 27 26 25 9 10 11 12 13 14 15 16
37
RZ10 R8 R7 R6 R5 R4 R3 R2 R1 22 8 7 6 5 4 3 2 1 DY4 DY5 DY6 DY7 DY8 DY9 DY10 DY11
13
14
15
16
17
18
19
20
21
22 GND
23
GND C39 0.1 F
VOL
Figure 18b. Evaluation Board Schematic (continued)
REV. A
-25-
24
AD9430
Figure 19. PCB Top Side Silkscreen
Figure 22. PCB Split Power Plane
Figure 20. PCB Top Side Copper
Figure 23. PCB Bottom Side Copper
Figure 21. PCB Ground Layer
Figure 24. PCB Bottom Side Silkscreen
-26-
REV. A
AD9430
OUTLINE DIMENSIONS 100-Lead Thin Plastic Quad Flat Package, Exposed Pad [TQFP/EP] (SV-100)
Dimensions shown in millimeters
0.75 0.60 0.45 SEATING PLANE 1.20 MAX
100 1
16.00 SQ 14.00 SQ
76 75 75 76 100 1
TOP VIEW
(PINS DOWN)
CONDUCTIVE HEAT SINK
25 26 49 50 50 49 26 25
0.20 0.09 7 3.5 0 0.50 BSC 0.27 0.22 0.17
1.05 1.00 0.95
6.50 NOM
0.15 0.05
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MS-026AED-HD NOTES 1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. 2. THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
REV. A
-27-
AD9430 Revision History
Location 3/03--Data Sheet changed from REV. 0 to REV. A. Page
Upgraded for AD9430-210 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Change to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Edits to Output Propagation Delay section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Added TPCs 5-8, 10-12, 14, 16, 18, 20, 22, 27, 31-32, 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Changes to TPCs 17, 19, 26, 35-36, 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Added text to ENCODE INPUT section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Added DS INPUTS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Change to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Changes to LVDS Outputs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Changes to Voltage Reference section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Replaced Figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Change to Troubleshooting section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
C02607-0-3/03(A) PRINTED IN U.S.A.
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
-28-
REV. A

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